1. Field of the Invention
The present invention relates to semiconductor device manufacturing, and more particularly to a method of forming a resistor within a thin vertically oriented semiconductor body (Fin) as well as the semiconductor structure this is formed by the inventive method. The present invention also provides a method of controlling the resistance of a plurality of vertically oriented semiconductor bodies as well as a method to eliminate the nominal variation on the Fin thickness from the variation on threshold voltage.
Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of metal oxide semiconductor field effect transistor (MOSFET) devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease of threshold voltage Vt in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain diffusion regions.
To scale down MOSFET channel lengths without excessive short-channel effects, gate oxide thickness has to be reduced while increasing channel-doping concentration. However, Yan, et al., “Scaling the Si MOSFET: From bulk to SOI to bulk”, IEEE Trans. Elect. Dev., Vol. 39, p. 1704, July 1992, have shown that to reduce short-channel effects for sub-0.05 μm MOSFETs, it is important to have a backside-conducting layer present in the structure that screens the drain field away from the channel. The Yan, et al. results show that double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.
The structure of a typical prior art double-gated MOSFET consists of a very thin vertical Si layer (Fin) for the channel, with two gates, one on each side of the channel. The term “Fin” is used herein to denote a semiconducting material which is employed as the body of the FET. The two gates are electrically connected so that they serve to modulate the channel. Short-channel effects are greatly suppressed in such a structure because the two gates very effectively terminate the drain field line preventing the drain potential from being felt at the source end of the channel. Consequently, the variation of the threshold voltage with drain voltage and with gate length of a prior art double-gated MOSFET is much smaller than that of a conventional single-gated structure of the same channel length.
Resistors are devices that have electrical resistance associated therewith. Resistors are typically employed in an electrical device for protection, operation and/or current control. Hence, resistors play an important part in current analog and digital circuit designs. To date, however, there are no known Fin structures that include a resistor built within the Fin of the structure. Using a Fin-based technology would require a redesign of current CMOS (complementary metal oxide semiconductor) resistor schemes for buried resistors (BRs), overpass resistors (Ops) and silicide resistors.
In view of the above, there is a need for providing Fin structures which include a resistor built within the thin vertical semiconductor body of the structure that do not require redesign of current CMOS resistor schemes.